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EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Features
* * * * * * * * * * * 4ns typ. propagation delay 5V to 12V input supply +2.7V to +5V output supply True-to-ground input Rail-to-rail outputs Separate analog and digital supplies Active low latch Single (EL5185C) available Dual (EL5285C) available Window available (EL5287C) Pin-compatible 8ns family available (EL5x81C, EL5283C & EL5482C)
General Description
The EL5485C and EL5486C comparators are designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications. The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5485C and EL5486C can be used to hold the comparator output value by applying a low logic level to the pin. The EL5485C is available in the 16-pin SO package and the EL5486C in the 24-pin QSOP package. Both are specified for operation over the full -40C to +85C temperature range. Also available are single (EL5185C), dual (EL5285C), and window comparator (EL5287C) versions.
Applications
* * * * * * Threshold detection High speed sampling circuits High speed triggers Line receivers PWM circuits High speed V/F converters
Pin Configurations
INA- 1 INA+ 2 NC 3 GND 4 INA- 1 INA+ 2 GND 3 OUTA 4 OUTB 5 VS- 6 INB+ 7 INB- 8 EL5485CS (16-Pin SO) + + 16 IND15 IND+ 14 VS+ 13 OUTD 12 OUTC 11 VSD 10 INC+ 9 INCLATCHA 5 OUTA 6 OUTB 7 LATCHB 8 VS- 9 NC 10 INB+ 11 INB- 12 EL5486CU (24-Pin QSOP) + +
24 IND23 IND+ 22 NC 21 VS+ 20 LATCHD 19 OUTD 18 OUTC 17 LATCHC 16 VSD 15 NC
Ordering Information
Part No EL5485CS EL5485CS-T7 EL5485CS-T13 EL5486CU EL5486CU-T13 Package 16-Pin SO 16-Pin SO 16-Pin SO 24-Pin QSOP 24-Pin QSOP Tape & Reel 7" 13" 13" Outline # MDP0027 MDP0027 MDP0027 MDP0040 MDP0040
+
-
-
+
+
-
-
+
September 7, 2001
14 INC+ 13 INC-
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
(c) 2001 Elantec Semiconductor, Inc.
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Absolute Maximum Ratings (T
A
= 25C)
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied Analog Supply Voltage (VS+ to VS-) +12.6V Digital Supply Voltage (VSD to GND) +7V Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Common-Mode Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage Storage Temperature Range Ambient operating Temperature Operating Junction Temperature Power Dissipation ESD Voltage
-0.2V to [(VSD) +0.2V] -65C to +150C -40C to +85C 125C TBDmW 2kV
Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VS = 5V, VSD = 5V, RL = 2.3k, CL = 15pF, TA = 25C, unless otherwise specified. Parameter Input VOS IB CIN IOS VCM CMRR Output VOH VOL tpd+ tpdSupply IS + IS ISD PSRR Latch VLH VLL ILH ILL td+ tdts th tpw(D) Latch Input Voltage High Latch Input Voltage Low Latch Input Current High Latch Input Current Low Positive Going Delay Time Negative Going Delay Time Minimum Setup Time Minimum Hold Time Minimum Latch Disable Pulse Width VLH = 3.0V VLL = 0.3V VOD = 5mV, CL = 15pF, IO = 2mA VOD = 5mV, CL = 15pF, IO = 2mA 0.8 -30 -30 -18 -24 4 4 2 1 5 2.0 V V A A ns ns ns ns ns Positive Analog Supply Current Negative Analog Supply Current Digital Supply Current Power Supply Rejection Ratio (per comparator) (per comparator) (per comparator) All inputs high (per comparator) All inputs low -60 12 7.5 5.5 0.9 -80 13 8.5 6.5 1.2 mA mA mA mA dB Output High Voltage Output Low Voltage Latch Disable to High Delay Latch Disable to Low Delay VIN > 250mV VIN > 2 50mV VIN = 1VP-P, VOD = 50mV VIN = 1VP-P, VOD = 50mV VSD - 0.6 VSD - 0.4 GND + 0.25 4 4 GND + 0.5 6 6 V V ns ns Input Offset Voltage Input Bias Current Input Capacitance Input Offset Current Input Voltage Range Common-mode Rejection Ratio -5V < V CM < +2.75V, VO = 2.5V VCM = 0V, VO = 2.5V -2.5 (VS-) - 0.1 -65 -90 VCM = 0V, VO = 2.5V -10 1 -5 5 0.5 2.5 (VS+) - 2.25 4 mV A pF A V dB Description Condition Min Typ Max Unit
Dynamic Performance
2
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Typical Performance Curves
Propagation Delay vs Overdrive VIN=5VSTEP VS=5V VSD=5V RL=2.2k Delay Time (ns) Propagation Delay vs Source Resistance VIN=1VSTEP VS=5V VSD=5V VOD=50mV RL=2.2k
7.8 7.6
15 13 11
TPD7.4 Delay Time (ns) 7.2 TPD+ 7 6.8 6.6 6.4 0.2
TPD9 TPD+ 7 5
0.6
1
1.4 VOD (V)
1.8
2.2
2.6
0
0.4
0.8
1.2
1.6
2
Source Resistance (k) Output High Voltage vs Temperature 4.832 4.83 4.828
10 8 6 4 2 0
Supply Current vs Supply Voltage (per comparator) VIN=50mV RL=2.2k
IS+
IS (mA)
I S-
VOH (V) 4 5 6
4.826 4.824 4.822 4.82 4.818 -50
0
1
2
3 VS (V)
-30
-10
10
30
50
70
90
Temperature (C) Input Bias Current vs Temperature 8 7 6
Offset Voltage vs Temperature 3 2.5 2 VOS (mV) 1.5 1 0.5 0 -50 IB (A) -30 -10 10 30 50 70 90
5 4 3 2 1 0 -50 -30 -10 10 30 50 70 90
Temperature (C)
Temperature (C)
3
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Typical Performance Curves
Output Low Voltage vs Temperature 0.285 0.275 Supply Current (mA) 0.265 0.255 0.245 0.235 -50 12 11 10 9 8 7 6 -50 ISSupply Current vs Temperature (per comparator)
I S+
VOL (V)
-30
-10
10
30
50
70
90
-30
-10
10
30
50
70
90
Temperature (C) Propagation Delay vs Supply Voltage 6.8 6.6 6.4 6.2 6 5.8 5.6 TPD+ 5 0 ISD (mA) 15 10 VSD=VS+ VOD=50mV RL=2.2k 25 20
Temperature (C) Digital Supply Current vs Switching Frequency (per comparator) VS=5V TA=25C
Delay Time (ns)
VSD=5V VSD=3V
TPD-
4
4.2
4.4
4.6
4.8
5 VS (V)
5.2
5.4
5.6
5.8
6
0
10
20
30
40
50
Frequency (MHz) Propagation Delay vs Overdrive VIN=3VSTEP VS=5V VSD=5V RL=2.2k TPD-
6.1 6 5.9 Delay Time (ns) 5.8 5.7 5.6 5.5 5.4 5.3
Propagation Delay vs Overdrive VIN=1VSTEP VS=5V VSD=5V RL=2.2k Delay Time (ns) TPD-
8 7.5 7 6.5
TPD+ 6 5.5 5 0.2
TPD+
5.2 50
100 150 200 250 300 350 400 450 500 550 600 VOD (mV)
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOD (mV)
4
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Typical Performance Curves
Propagation Delay vs Load Capacitance VIN=1VSTEP VS=5V VSD=5V VOD=50mV RL=2.2k TPDPower Dissipation vs Ambient Temperature 1.4 1.2 Power Dissipation (W) 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 85 100 125 150 CLOAD (pF) Output with 50MHz Input VIN=1VP-P Ambient Temperature (C) Output with 50MHz Input VIN=3VP-P 909mW 1087mW
QS OP 24
SO 16
9 8.5 8 Delay Time (ns) 7.5 7 6.5 6 5.5 5
11 5
C /W
JA =
TPD+
11 0 C/ W
Output (5ns/div, 2V/div) Input (5ns/div, 0.5nV/div)
Output (5ns/div, 2V/div) Input (5ns/div, 2V/div)
5
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Timing Diagram
Compare Latch Enable Input Latch Differential Input Voltage ts VIN VOS VOD tpdtd+ th Compare
1.4V Latch tpw(D) Latch
Comparator Output
2.4V
Definition of Terms
Term VOS VIN VOD tpd+ tpdtd+ tdts th tpw (D) Definition Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change
6
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Pin Descriptions
EL5485C 16-Pin SO (0.150") 1 EL5486C 24-Pin QSOP 1 Pin Name INAFunction Negative input, channel A Equivalent Circuit
VS+
IN-
IN+
VSCircuit 1
2 3
2 3,10,15,22 4 5
INA+ NC GND LATCHA
Positive input, channel A Not Connected Digital ground Latch input, channel A
(Reference circuit 1)
VS+
VSD
LATCH
VSCircuit 2
4
6
OUTA
Output, channel A
VSD
VS+
OUT
V SCircuit 3
5 6 7 8 9 10 11 12 13
7 8 9 11 12 13 14 16 17 18 19 20
OUTB LATCHB VSINB+ INBINCINC+ VSD LATCHC OUTC OUTD LATCHD
Output, channel B Latch input, channel B Negative supply voltage Positive input, channel B Negative input, channel B Negative input, channel C Positive input, channel C Digital supply voltage Latch input, channel C Output, channel C Output, channel D Latch input, channel D
(Reference circuit 3) (Reference circuit 2) (Reference circuit 1) (Reference circuit 1) (Reference circuit 1) (Reference circuit 1) (Reference circuit 2) (Reference circuit 3) (Reference circuit 3) (Reference circuit 2)
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EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Pin Descriptions
EL5485C 16-Pin SO (0.150") 14 15 16 EL5486C 24-Pin QSOP 21 23 24 Pin Name VS+ IND+ INDFunction Positive supply voltage Positive input, channel D Negative input, channel D (Reference circuit 1) (Reference circuit 1) Equivalent Circuit
8
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Applications Information
Power Supplies and Circuit Layout
The EL5485C and EL5486C comparators operate with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7F tantalum in parallel with a 0.1F ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparators. imum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5485C and EL5486C, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate.
Latch Pin Dynamics
The EL5486C contains a "transparent" latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch's highto-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay). The EL5485C does not have latch inputs.
Input Voltage Considerations
The EL5485C and EL5486C's input range is specified from 0.1V below VS- to 2.25V below VS+. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage.
Hysteresis
Hysteresis can be added externally. The following two methods can be used to add hysteresis. Inverting comparator with hysteresis:
VREF R2 R1 VIN + R3
Input Slew Rate
Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain min9
R3 adds a portion of the output to the threshold set by R1 and R2 . The calculation of the resistor values are as follows:
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Select the threshold voltage VTH and calculate R1 and R2. The current through R1/R2 bias string must be many times greater than the input bias current of the comparator:
R1 V T H = V REF x ------------------R +R
1 2
The above two methods will generate hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to affect the bias string and adjustment of R1 may be required.
Power Dissipation
When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125C). An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small:
P DISS = ( V S x I S + V SD x I SD )
Let the hysteresis be VH, and calculate R3:
VO R 3 = ------- x ( R 1 || R 2 ) VH
where: VO=VSD-0.8V (swing of the output) Recalculate R2 to maintain the same value of VTH:
V TH V T H - 0.5V SD R 2 1 = ( V REF - V T H ) / ----------- + ------------------------------------ R3 R1
where: VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator VSD is the digital supply voltage from VSD to ground ISD is the digital supply current per comparator ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows:
T JMAX = T MAX + JA x P DISS
Non inverting comparator with hysteresis:
R3 VIN R1 VREF + -
R3 adds a portion of the output to the positive input. Note that the current through R3 should be much greater than the input bias current in order to minimize errors. The calculation of the resistor values as follows: Pick the value of R1. R1 should be small (less than 1k) in order to minimize the propagation delay time. Choose the hysteresis VH and calculate R3:
R1 R 3 = ( V SD - 0.8 ) x ------VH
where: TMAX is the maximum ambient temperature JA is the thermal resistance of the package
Threshold Detector
Check the current through R3 and make sure that it is much greater than the input bias current as follows:
0.5VSD - V REF I = --------------------------------------R3
The inverting input is connected to a reference voltage and the non-inverting input is connected to the input. As the input passes the VREF threshold, the comparator's
10
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
output changes state. The non-inverting and inverting inputs may be reversed. back to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz over a 2V to 7V supply range. The output duty cycle for this circuit is roughly 50% at 5V VCC, but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by changing VCC value.
5V 1MHz to 8MHz
VIN VREF
+ -
VOUT
Crystal Oscillator
A simple crystal oscillator using one comparator of an EL5485C and EL5486C is shown below. The resistors R1 and R2 set the bias point at the comparator's noninverting input. Resistors R3, R4, and C1 set the inverting input node at an appropriate DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5485C and EL5486C will give the correct logic output when an input is outside the common mode range, additional delays may occur when it is so operated. Therefore, the DC bias voltages at the inputs are set about 500mV below the center of the common mode range and the 200 resistor attenuates the feed-
200 5k 1.5k C1 + R4 2k
R1 R2
VOUT R3 2k
0.01F
11
EL5485C, EL5486C - Preliminary
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
September 7, 2001
Elantec Semiconductor, Inc.
675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323 (888) ELANTEC Fax: (408) 945-9305 European Office: +44-118-977-6020 Japan Technical Center: +81-45-682-5820
12
Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.'s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Printed in U.S.A.

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